SPI General Operations
6-8 ADSP-21368 SHARC Processor Hardware Reference
SPI General Operations
The SPI in the ADSP-21367/8/9 and ADSP-2137x processors can be used
in a single master as well as in a multimaster environment. In both of
these configurations, every MOSI pin in the SPI system is connected. Like-
wise, every
MISO pin in the system is on a single node, and every SPICLK
pin is connected. SPI transmission and reception are always enabled
simultaneously, unless broadcast mode has been selected. In broadcast
mode, several slaves can be configured to receive from the master, but only
one of the slaves can be in transmit mode. This is done by driving the MISO
line, to communicate back with the master. If the transmit or receive is
not needed, MISO can be ignored and does not need to be connected. This
section describes the clock signals, SPI operation as a master and as a slave,
and error generation conditions.
Figure 6-4. SHARC Processor as SPI Master and Slave
8-bit Host
MICROCONTROLLER
ADSP-213xx
ADSP-213xx AD1855
SPI SLAVE DEVICE
MASTER DEVICE STEREO 96 KHz DAC
SPICLK
SPIDS
MOSI
MISO
CCLK
CLATCH
DATA
FLAG0
S_SEL
SCLK
MOSI
MISO
SPICLK
MOSI
SHARC Processor as SPI Master
SHARC Processor as SPI Slave
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