Data Delays, Latencies, and Throughput
14-52 ADSP-21368 SHARC Processor Hardware Reference
Booting From an SPI PROM (16-Bit address)
Figure 14-16 shows the initial 32-bit word sent out from the processor
from the perspective of the serial PROM device.
As shown in Figure 14-16, SPI EEPROMS only require an 8-bit opcode
and a 16-bit address. These devices begin transmitting on clock cycle 24.
However, because the processor is not expecting data until clock cycle 32,
it is necessary to pad an extra byte to the beginning of the boot stream
when programming the PROM. In other words, the first byte of the ker-
nel is the second byte of the boot stream. The VisualDSP++ tools
automatically handles this in the loader file generation process for SPI
PROM devices.
Booting From an SPI Host Processor
Typically, host processors in SPI slave mode transmit data on every
SPICLK
cycle. This means that the first four bytes that are sent by the host proces-
sor are part of the first 32-bit word that is thrown away by the processor
(see Figure 14-16). Therefore, it is necessary to pad an extra four bytes to
the beginning of the boot stream when programming the host. For exam-
ple, the first byte of the kernel is the fifth byte of the boot stream.
VisualDSP++ automatically handles this in the loader file generation
process.
Data Delays, Latencies, and Throughput
Table 14-15 specifies latencies and throughput for the ADSP-21367/8/9
and ADSP-2137x processors. Latency is defined as the number of cycles,
after the first cycle, required to complete the operation. A zero wait state
memory has a latency of zero. A single wait state memory has a data delay
of one. Throughput is the maximum rate at which the operation is per-
formed. Data delay and throughput are the same whether the access is
from a host processor or from another SHARC processor.
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