FIFO to Memory Data Transfer
7-30 ADSP-21368 SHARC Processor Hardware Reference
5. Read the
DAI_IRPTL_L or DAI_IRPTL_H registers to see if more inter-
rupts have been generated.
• If the value(s) are not zero, repeat step 4.
• If the value(s) are zero, continue to step 6.
6. Re-enable the IDP_DMA_EN bit in the IDP_CTL0 register (set to 1).
7. Exit the ISR.
If a zero is read in step 5 (no more interrupts are latched), then all of the
interrupts needed for that ISR have been serviced. If another DMA com-
pletes after step 5 (that is, during steps 6 or 7), as soon as the ISR
completes, the ISR is called again because the OR of the latched bits will
be nonzero again. DMAs in process run to completion.
L
If step 5 is not performed, and a DMA channel expires during step
4, then when IDP DMA is re-enabled (step 6), the completed
DMA will not have been reprogrammed and its buffer will overrun.
FIFO Overflow
If the data out of the FIFO (either through DMA or core reads) is not suf-
ficient to transfer at the combined data rate of all the channels, then a
FIFO overflow can occur. When this happens, new data is not accepted.
Additionally, data coming from the serial input channels (except for
32-bit I
2
S and left-justified modes) are not accepted in pairs, so that alter-
nate data from a channel is always from left and right channels. If overflow
occurs, then sticky bits in the DAI_STAT register are set and an interrupt is
generated. Data is accepted again when space has been created in the
FIFO.
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