Configuring Peripherals Using SRU2
4-72 ADSP-21368 SHARC Processor Hardware Reference
Configuring the PCGs
“Precision Clock Generators” on page 13-1 provides extensive informa-
tion on programming using the DAI. “Clock and Frame Sync Divisors
PCG Channel B” on page 13-20 is an example program that uses PCG
channel B to output a clock on DAI pin 1 and a frame sync on DAI pin 2.
Configuring Peripherals Using SRU2
The following sections describe how the various peripherals associated
with SRU2 are configured.
Configuring the SPI
All SPI signals are routed through the SRU2 and are routed as described
in “Signal Routing Units” on page 4-8, Figure 4-3 on page 4-6 and
Figure 4-4 on page 4-7. Normally, it is acceptable to enable (SRU2) out-
put buffers to permanently ground the pin enable signals. However, this
does not work for the open-drain mode, because the SRU2 buffer always
actively drives the output pin. Where open-drain mode is used, the pin
enable signals must be connected to the pin enable associated with the SPI
SRU2 buffers and connected with the SPIB_MISO_O, SPIB_MOSI_O,
SPIB_CLK_O, and SPIB_FLGx_O pins. For more information on open-drain
mode, see “Open Drain Mode (OPD)” on page 6-9.
Choosing the Pin Enable for the SPI Clock
When in SPI master mode, the
SPICLK signal is sent from the processor.
The enable signal for the DPI pin being used for the clock must be con-
nected correctly depending on the SPI mode being used (based on the
setting of CPHASE and CLKPL bits in the SPICTL register). Table 4-14 shows
the correct pin enable to use by SPI mode.
To Next Page
Loading...
Need help?
General
