Frame Sync Outputs
13-4 ADSP-21368 SHARC Processor Hardware Reference
The
CLKASOURCE bit (bit 31 in the PCG_CTLA1 registers) specifies the input
source for the clock of the respective units (A, B, C, and D). When this bit
is cleared (= 0), the input is sourced from the external oscillator, as shown
in Figure 13-1. When set (= 1), the input is sourced from SRU1, as speci-
fied in the PCG_EXTA_I bits in the SRU_CLK4 register. The CLKASOURCE bit is
overridden if CLKA_SOURCE_IOP bit (bit 2) in the PCG_SYNC register is set. If
the CLKA_SOURCE_IOP bit is set, the input is sourced from the peripheral
clock. See “Group A Connections—Clock Signals” on page 4-19.
The PCG units B, C, and D function identically, except that the
PCG_CTLB1, PCG_CTLC1, and PCG_CTLD1 bits (bit 31) indicate that the exter-
nal source for these units is specified in PCG_EXTB_I, PCG_EXTC_I, and
PCG_EXTD_I bits in the SRU_CLK4 and SRU_CLK5 registers. See Figure 4-16
on page 4-22 and Figure 4-17 on page 4-23.
Note that the clock output is always set (as closely as possible) to a 50%
duty cycle. If the clock divisor is even, the duty cycle of the clock output is
exactly 50%. If the clock divisor is odd, then the duty cycle is slightly less
than 50%. The low period of the output clock is one input clock period
more than the high period of the output clock. For higher values of an
odd divisor, the duty cycle is close to 50%.
L
A PCG clock output cannot be fed to its own input. Setting
SRU_CLK4[4:0] = 0x1C connects PCG_EXTA_I to logic low, not
PCG_CLKA_O. Setting SRU_CLK4[9:5] = 0x1D connects PCG_EXTB_I
to logic low, not PCG_CLKB_O.
Frame Sync Outputs
Each of the four units (A through D) also produces a synchronization sig-
nal for framing serial data. The frame sync outputs are much more flexible
since they need to accommodate the wide variety of serial protocols used
by peripherals.
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