ADSP-21368 SHARC Processor Hardware Reference 4-23
Digital Audio/Digital Peripheral Interfaces
Figure 4-17. SRU_CLK5 Register
Table 4-4. Group A Sources—Serial Clock
Selection Code Source Signal Description (Source)
00000 (0x0) DAI_PB01_O Select DAI pin buffer 1
00001 (0x1) DAI_PB02_O Select DAI pin buffer 2
00010 (0x2) DAI_PB03_O Select DAI pin buffer 3
00011 (0x3) DAI_PB04_O Select DAI pin buffer 4
00100 (0x4) DAI_PB05_O Select DAI pin buffer 5
00101 (0x5) DAI_PB06_O Select DAI pin buffer 6
00110 (0x6) DAI_PB07_O Select DAI pin buffer 7
00111 (0x7) DAI_PB08_O Select DAI pin buffer 8
01000 (0x8) DAI_PB09_O Select DAI pin buffer 9
01001 (0x9) DAI_PB10_O Select DAI pin buffer 10
01010 (0xA) DAI_PB11_O Select DAI pin buffer 11
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1001111011110111
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0011110111101111
PCG_SYNC_CLKC_I
Precision Clock Generator
Clock C Sync Input
SPORT6_CLK_I
Serial Port 6 Clock Input
SPORT7_CLK_I
Serial Port 7 Clock Input
SRU_CLK5 (0x2435)
PCG_SYNC_CLKD_I
Precision Clock Generator
Clock D Sync Input
PCG_EXTC_I
Reset = 0x3DEF7BDE
PCG_SYNC_CLKD_I
Precision Clock Generator
External Clock C Input
PCG_EXTD_I
Precision Clock Generator
External Clock D Input
Precision Clock Generator
Clock D Sync Input