Making Connections in the SRUs
4-24 ADSP-21368 SHARC Processor Hardware Reference
01011 (0xB) DAI_PB12_O Select DAI pin buffer 12
01100 (0xC) DAI_PB13_O Select DAI pin buffer 13
01101 (0xD) DAI_PB14_O Select DAI pin buffer 14
01110 (0xE) DAI_PB15_O Select DAI pin buffer 15
01111 (0xF) DAI_PB16_O Select DAI pin buffer 16
10000 (0x10) DAI_PB17_O Select DAI pin buffer 17
10001 (0x11) DAI_PB18_O Select DAI pin buffer 18
10010 (0x12) DAI_PB19_O Select DAI pin buffer 19
10011 (0x13) DAI_PB20_O Select DAI pin buffer 20
10100 (0x14) SPORT0_CLK_O Select SPORT 0 Clock
10101 (0x15) SPORT1_CLK_O Select SPORT 1 Clock
10110 (0x16) SPORT2_CLK_O Select SPORT 2 Clock
10111 (0x17) SPORT3_CLK_O Select SPORT 3 Clock
11000 (0x18) SPORT4_CLK_O Select SPORT 4 Clock
11001 (0x19) SPORT5_CLK_O Select SPORT 5 Clock
11010 (0x1A) DIR_CLK_O Select SPDIF receive clock output
11011 (0x1B) DIR_TDMCLK_O Select SPDIF receive TDM clock output
11100 (0x1C) PCG_CLKA_O Select precision clock A output
11101 (0x1D) PCG_CLKB_O Select precision clock B output
11110 (0x1E) LOW Select logic level low (0)
11111 (0x1F) HIGH Select logic level high (1)
Table 4-4. Group A Sources—Serial Clock (Cont’d)
Selection Code Source Signal Description (Source)
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