PWM Registers
8-18 ADSP-21368 SHARC Processor Hardware Reference
PWM Registers
The registers described below control the operation and provide the status
of pulse width modulation on the ADSP-21367/8/9 and ADSP-2137x
processors. For more information, see “Pulse Width Modulation Regis-
ters” on page A-78.
• PWM global control register. The PWMGCTL register enables or dis-
ables the four PWM groups in any combination. This provides
synchronization across the four PWM groups. This 16-bit,
read/write register is located at address 0x3800.
• PWM global status register. The PWMGSTAT register provides the
status of each PWM group and is located at address 0x3801. The
bits in this register are W1C-type (write one-to-clear).
• PWM control registers. The
PWMCTL3–0 registers are used to set the
operating modes of each PWM block. These registers also allow
programs to disable interrupts from individual groups.
• PWM status registers. The PWMSTAT3–0 registers are 16-bit
read-only registers report the status of the phase and mode for each
PWM group.
11 24.4 48.8
12 12.2 24.4
13 6.1 12.2
14 3.05 6.1
Table 8-1. PWM Accuracy in Single and Double-Update Modes (Cont’d)
Resolution (bits) Single-Update Mode
PWM Frequency (kHz)
Double-Update Mode
PWM Frequency (kHz)
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