PWM Implementation
8-8 ADSP-21368 SHARC Processor Hardware Reference
Duty Cycles and Dead Time
A typical pair of PWM outputs (in this case for
pwm_ah and pwm_al) from
the timing unit are shown in Figure 8-2 for operation in single-update
mode. All illustrated time values indicate the integer value in the associ-
ated register and can be converted to time by simply multiplying by the
fundamental time increment, (t
PCLK
) and comparing this to the
two’s-complement counter. Note that the switching patterns are perfectly
symmetrical about the midpoint of the switching period in single-update
mode since the same values of the PWMAx, PWMPERIODx, and PWMDTx registers
are used to define the signals in both half cycles of the period. Further, the
programmed duty cycles are adjusted to incorporate the desired dead time
into the resulting pair of PWM signals. As shown in Figure 8-2, the dead
time is incorporated by moving the switching instants of both PWM sig-
nals (pwm_ah and pwm_al) away from the instant set by the PWMAx registers.
Both switching edges are moved by an equal amount (PWMDT x t
PCLK
)
to preserve the symmetrical output patterns. Also shown is the PWM_PHASE
bit of the PWMSTAT register that indicates whether operation is in the first
or second half cycle of the PWM period.
To Next Page
Loading...
Need help?
General
