Register Descriptions
12-4 ADSP-21368 SHARC Processor Hardware Reference
The clock generation module is used to generate an external serial clock
(
SCL) when in master mode. It includes the logic necessary for synchroni-
zation in a multimaster clock configuration and clock stretching when
configured in slave mode.
Register Descriptions
The TWI controller has 16 registers which are described in the following
sections. More information on these registers can be found in “Two Wire
Interface Registers” on page A-130.
TWI Master Internal Time Register
The TWI control register (TWIMITR) is used to enable the TWI module as
well as to establish a relationship between the peripheral clock (PCLK) and
the TWI controller’s internally-timed events. The internal time reference
is derived from PCLK using a prescaled value.
PRESCALE = f
PCLK
/10 MHz
Additional information for the TWIMITR register bits includes:
TWI Enable (TWIEN). This bit must be set for slave or master mode opera-
tion. It is recommended that this bit be set and remain set at the time
PRESCALE is initialized. This guarantees accurate operation of bus busy
detection logic.
Prescale (
PRESCALE). This value should be set to the number of peripheral
clock periods that equals the time period corresponding to a 10 MHz fre-
quency. This number is represented as a 7-bit binary value.
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