ADSP-21368 SHARC Processor Hardware Reference 5-67
Serial Ports
L
When the SPORT is configured as a transmitter, these bits reflect
transmit buffer status for the TXSPxA and TXSPxB buffers. When the
SPORT is configured as a receiver, these bits reflect receive buffer
status for the RXSPxA and RXSPxB buffers.
Transmit and Receive Data Buffers
(TXSPxA/B, RXSPxA/B)
The transmit buffers (TXSP0A–TXSP7A and TXSP0B–TXSP7B) are the 32-bit
transmit data buffers for SPORT0 through SPORT7 respectively. These
buffers must be loaded with the data to be transmitted if the SPORT is
configured to transmit on the A and B channels. The data is loaded auto-
matically by the DMA controller or loaded manually by the program
running on the processor core.
The receive buffers (RXSP0A–RXSP7A and RXSP0B–RXSP7B) are the 32-bit
receive data buffers for SPORT0 through SPORT7 respectively. These
32-bit buffers become active when the SPORT is configured to receive
data on the A and B channels. When a SPORT is configured as a receiver,
the RXSPxA and RXSPxB registers are automatically loaded from the receive
shifter when a complete word has been received. The data is then loaded
to internal memory by the DMA controller or read directly by the pro-
gram running on the processor core.
L
Word lengths of less than 32 bits are automatically right-justified
in the receive and transmit buffers.
The transmit buffers act like a two-location FIFO because they have a data
register plus an output shift register. Two 32-bit words may both be
stored in the transmit queue at any one time. When the transmit register is
loaded and any previous word has been transmitted, the register contents
are automatically loaded into the output shifter. An interrupt occurs when
the output transmit shifter has been loaded, signifying that the transmit
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