SPORT Control Registers and Data Buffers
5-66 ADSP-21368 SHARC Processor Hardware Reference
Specifically, the operation of the
ROVF bit is:
• 0 = No new data while RXSPxA/B buffer is full.
• 1 = New data while RXSPxA/B buffer is full.
When the DIFS bit is cleared (the default setting), the frame sync signal
(SPORTx_FS) is dependent upon new data being present in the transmit
buffer. The SPORTx_FS signal is only generated for new data. Setting DIFS
to 1 selects data-independent frame syncs which causes the SPORTx_FS sig-
nal to be generated whether or not new data is present. With each
SPORTx_FS signal, the SPORT transmits the contents of the transmit
buffer. Serial port DMA typically keeps the transmit buffer full. The DIFS
bit is not applicable for multichannel mode.
L
In the ADSP-21367/8/9 and ADSP-2137x processors, programs
no longer need to poll these registers to detect an underflow or
overflow condition. Instead, an interrupt is generated and pro-
grams only need to read the new SPORT error status register
(SPERRSTAT) to determine what register contains the error and what
the error is. For more information, see “Frame Sync Error Detec-
tion” on page 5-42.
Data buffer status. SPCTLx registers, bits 31–30 (DXS_A) and bits 28-27
(DXS_B). These read-only bits indicate the status of the SPORT’s data
buffer as follows: 11 = buffer full, 00 = buffer empty, 10 = buffer partially
full, 01 = reserved.
The DXS_A or DXS_B status bits indicate whether the TXSPxA/RXSPxA or
TXSPxB/RXSPxB buffer is full (11), empty (00), or partially full (10). To
test for space in
TXSPxA/B or RXSPxA/B, test whether DXS_A (bit 30) is equal
to zero for the A channel, or whether DXS_B (bit 27) is equal to zero for the
B channel. To test for the presence of any data in
TXSPxA/B or RXSPxA/B,
test whether
DXS_A (bit 31) is equal to one for the A channel, or whether
DXS_B (bit 28) is equal to one for the B channel. This description applies
to all operating modes.
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