Interrupt Registers
B-6 ADSP-21368 SHARC Processor Hardware Reference
Interrupt Registers
This section provides information on the registers that are used to config-
ure and control interrupts. These registers are:
• “Interrupt Register (LIRPTL)” on page B-6
• “Interrupt Latch Register (IRPTL)” on page B-13
• “Interrupt Mask Register (IMASK)” on page B-18
• “Interrupt Mask Pointer Register (IMASKP)” on page B-22
Interrupt Register (LIRPTL)
The LIRPTL register is a non-memory-mapped, universal, system register
(Ureg and Sreg). The reset value for these registers is 0x0000 0000. The
LIRPTL register indicates latch status, select masking, and displays mask
pointers for interrupts. Figure B-1, Figure B-2, and Table B-4 provide bit
definitions for the LIRPTL register.
[
The MSKP bits in the LIRPTL register and the entire IMASKP register
are for interrupt controller use only. Modifying these bits interferes
with the proper operation of the interrupt controller.
The interrupt bits 0 through 19 are programmable through the program-
mable interrupt controller registers (
PICRx). The descriptions provided are
their default sources. For information on their optional use, see “Periph-
eral Interrupt Priority Control Registers” on page A-164.
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