Interrupt Registers
B-8 ADSP-21368 SHARC Processor Hardware Reference
Figure B-2. LIRPTL Register (Bits 0–15)
Table B-4. LIRPTL Register Bit Descriptions
Bit Name Description
0 P6I (SP01) Programmable Interrupt 6 (SPORT 0 Interrupt). Indicates
if an SP0I interrupt is latched and is pending (if set, = 1), or
no SP0I is pending (if cleared, = 0). An SP0I interrupt occurs
two cycles after the last bit of an input/output serial word is
latched into/from RXSP0A/TXSP0A, RXSP0B/TXSP0B.
1 P7I (SP2I) Programmable Interrupt 7 (SPORT 2 Interrupt). Indicates
if an SP2I interrupt is latched and is pending (if set, = 1), or
no SP2I is pending (if cleared, = 0). An SP2I interrupt occurs
two cycles after the last bit of an input/output serial word is
latched into/from RXSP2A/TXSP2A, RXSP2B/TXSP2B.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
P13I
P11IMSK
P9IMSK
P10I
Programmable Interrupt 10
(General-Purpose IOP
Timer1 Interrupt 0x54)
P11I
Programmable Interrupt 12
(DAI Low Priority Interrupt
0x5C)
P12I
P10IMASK
Programmable Interrupt 10 Mask
(General-purpose IOP Timer1
Interrupt Mask)
P8IMSK
Programmable Interrupt 8 Mask
(SPORT4 Interrupt Mask)
Programmable Interrupt 9 Mask
(External Port DMA Channel 0
Interrupt Mask)
P7IMSK
Programmable Interrupt 7 Mask
(SPORT2 Interrupt Mask)
P6IMSK
Programmable Interrupt 6 Mask
(SPORT0 Interrupt Mask)
P18I
Programmable Interrupt 18
(SPI B Interrupt 0x74)
P6I
Programmable Interrupt 6
(SPORT0 Interrupt 0x44)
P7I
Programmable Interrupt 7
(SPORT2 Interrupt 0x48)
P8I
Programmable Interrupt 8
(SPORT4 Interrupt 0x4C)
P9I
Programmable Interrupt 9
(External Port DMA Chan-
nel 0 Interrupt 0x50)
P17I
Programmable Interrupt 17
(General-Purpose IOP
Timer2 Interrupt 0x70)
Programmable Interrupt 13
(External Port DMA Chan-
nel 1 Interrupt 0x60)
LIRPTL
Defaults in parenthesis
Programmable Interrupt 11
(SPORT7 Interrupt 0x5C)
Programmable Interrupt 11
Mask (SPORT7 Interrupt Mask)
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