Analog Devices SHARC ADSP-21368 - Page 839

ADSP-21368 SHARC Processor Hardware Reference B-9
Interrupts
2 P8I (SP4I) Programmable Interrupt 8 (SPORT 4 Interrupt). Indicates
if an SP4I interrupt is latched and is pending (if set, = 1), or
no SP4I is pending (if cleared, = 0). An SP4I interrupt occurs
two cycles after the last bit of an input/output serial word is
latched into/from RXSP4A/TXSP4A, RXSP4B/TXSP4B.
3 P9I (EPDMA0I) Programmable Interrupt 9 (External Port DMA Channel 0
Interrupt). Indicates if an external port interrupt (EPDMA0)
is latched and pending (if set, = 1), or that no external port
interrupt is pending (if cleared, = 0). An external port inter-
rupt occurs when the DMA block transfer has completed.
This interrupt also occurs during core-driven transfers when
the Tx buffer is not full or the Rx buffer is not empty.
4 P10I (GPTMR1I) Programmable Interrupt 10 (General-Purpose IOP Timer 1
Interrupt). Indicates if a GPTMR1I is latched and is pend-
ing (if set, = 1), if no GPTMR1I is pending (if cleared, = 0).
5 P11I (SP7I) Programmable Interrupt 11 (SPORT 7 Interrupt). Indicates
if an SP7I interrupt is latched and is pending (if set, = 1), or
no SP7I is pending (if cleared, = 0). An SP7I interrupt occurs
two cycles after the last bit of an input/output serial word is
latched into/from RXSP7A/TXSP7A, RXSP7B/TXSP7B.
6 P12I (DAI2I) Programmable Interrupt 12 (DAI2 Interrupt). Indicates if a
DAI2 interrupt is latched and is pending (if set, = 1) or no
DAI2 interrupt is pending (if cleared, = 0). This is the lower
priority option.
7 P13I (EPDMA1I) Programmable Interrupt 13 (External Port DMA Channel 1
Interrupt). Indicates if an external port interrupt (EPDMA1)
is latched and pending (if set, = 1), or that no external port
interrupt is pending (if cleared, = 0). An external port inter-
rupt occurs when the DMA block transfer has completed.
This interrupt also occurs during core-driven transfers when
the Tx buffer is not full or the Rx buffer is not empty.
8 P17I (GPTMR2I) Programmable Interrupt 17 (General-Purpose IOP Timer 2
Interrupt). Indicates if a GPTMR2I is latched and is pend-
ing (if set, = 1), or no GPTMR2I is pending (if cleared, = 0).
Table B-4. LIRPTL Register Bit Descriptions (Cont’d)
Bit Name Description