Serial Port Registers
A-44 ADSP-21368 SHARC Processor Hardware Reference
SPORT Receive Buffer Registers (RXSPx)
The 32-bit RXSPx registers hold the input data from serial port receive
operations. The reset value for these registers is undefined. For more
information on how receive buffers work, see “Transmit and Receive Data
Buffers (TXSPxA/B, RXSPxA/B)” on page 5-67. The addresses of the
RXSPx registers are:
SPORT Divisor Registers (DIVx)
The addresses of the DIVx registers are:
These registers, shown in Figure A-20, have an undefined reset value.
These registers contain two fields:
• Bits 15–1 are CLKDIV. These bits identify the serial clock divisor
value for internally-generated
SCLK as follows:
RXSP0A – 0xc61 RXSP0B – 0xc63
RXSP1A – 0xc65 RXSP1B – 0xc67
RXSP2A – 0x461 RXSP2B – 0x463
RXSP3A – 0x465 RXSP3B – 0x467
RXSP4A – 0x861 RXSP4B – 0x863
RXSP5A – 0x865 RXSP5B – 0x867
RXSP6A – 0x4861 RXSP6B – 0x4863
RXSP7A – 0x4865 RXSP7B – 0x4867
DIV0 – 0xc02 DIV1 – 0xc03
DIV2 – 0x402 DIV3 – 0x403
DIV4 – 0x802 DIV5 – 0x803
DIV6 – 0x4802 DIV7 – 0x4803
CLKDIV
f
CCLK
8 f
SCLK
()
-----------------------
1–=
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