Frame Sync Outputs
13-6 ADSP-21368 SHARC Processor Hardware Reference
sync appears to lead the clock. If the phase is only slightly less than the
divisor, then the frame sync appears to lag the clock. The frame sync phase
should not be greater than the divisor.
Bypass Mode
In bypass mode, the frame sync divisor is either 0 or 1. There are two ways
the bypass mode operates, depending on the
STROBEA, STROBEB, STROBEC
and
STROBED bits of the PCG_PW and PCG_PW2 registers of the pulse width
control register (PCG_PWx, see Table A-66 on page A-159). This is shown
below.
• Direct bypass. If the STROBEA/B/C/D of the pulse width control reg-
ister (PCG_PW, PCG_PW2) is reset to 0, then the input is directly
passed to the frame sync output, either not inverted or inverted,
depending on the INVFSA, INVFSB, INVFSC and INVFSD bits of the
PCG_PW and PCG_PW2 registers.
• One-shot. In the bypass mode, if the least significant bit (LSB) of
the PCG_PW register is set to 1, then a one-shot pulse is generated.
This one-shot-pulse has a duration equal to the period of MISCA2_I
for unit A, MISCA3_I for unit B, MISCA4_I for unit C, and MISCA5_I
for unit D (see “Group E Connections—Interrupts and Miscella-
neous Signals” on page 4-43). This pulse is generated either at the
rising or at the falling edge of the input clock, depending on the
value of the INVFSA, INVFSB, INVFSC, and INVFSD bits of the PCG_PW
and PCG_PW2 registers.
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