AMI Timing Control
3-22 ADSP-21368 SHARC Processor Hardware Reference
enabled, the minimum value is
WS = 2 (a wait state value of 0 corresponds
to 32 wait cycles). The processor samples the ACK signal after the pro-
grammed wait state count expires—it is imperative that the WS value is
initialized when the acknowledge enable bit (ACKEN) is set.
Bus Idle Cycles
A bus idle cycle (IC bits 16–14 in the AMICTLx registers) is an inactive bus
cycle that the processor automatically generates to avoid data bus driver
conflicts. Such a conflict can occur when a device with a long output dis-
able time continues to drive after
RD is deasserted, while another device
begins driving on the following cycle. Idle cycles are also required to pro-
vide time for a slave in one bank to three-state its ACK driver, before the
slave in the next bank enables its ACK driver in synchronous access modes.
Figure 3-4 shows idle cycle insertion between a synchronous read and a
zero-wait, synchronous write in cycle 3.
To avoid this data bus driver conflict, the processor generates an idle cycle
in the following cases:
• On a transition from a read operation to a write operation
• On a transition from read from one bank to another bank
• On a transition from read from one bank to external access from
another device such as an SDRAM controller or another master in
a shared memory system
L
Unlike previous SHARC processors, the ADSP-21367/8/9 and
ADSP-2137x SHARC processors do not support idle cycle inser-
tion on a page boundary crossing. If an idle cycle is programmed
for a particular bank, then a minimum of one cycle is inserted for
reads, even if they are from the same bank.
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