FIFO to Memory Data Transfer
7-16 ADSP-21368 SHARC Processor Hardware Reference
IDP_BHD bit (= 1) prevents the core from hanging on reads from an empty
IDP_FIFO register. Clearing this bit (= 0) causes the core to hang under the
conditions described previously.
The IDP_FIFOSZ bits track the number of words in the FIFO. This 4-bit
field identifies the number of valid data samples in the IDP FIFO.
The SRU_OVF bits (bits 8–15) in the DAI_STAT register provide IDP FIFO
overflow status information for each of the channels. These bits are set
(= 1), whenever an overflow occurs. When these bits are cleared (= 0), it
indicates there is no overflow condition. These read-only bits are W1C
bits, which do not automatically reset to 0 when an overflow condition
changes to a no-overflow condition. These bits must be reset manually,
using the IDP_CLROVR bit in the IDP_CTL0 register. Writing one to this bit
clears the overflow conditions for the channels in the DAI_STAT register.
Since IDP_CLROVR is a write-only bit, it always returns low when read.
FIFO to Memory Data Transfer
The data from each of the eight IDP channels is inserted into an eight-reg-
ister deep FIFO, which can only be transferred to the core’s memory space
sequentially. Data is moved into the FIFO as soon as it is fully received.
When more than one channel has data ready, the channels access the
FIFO with fixed priority, from a low to high channel number (that is,
channel 0 is the highest priority and channel 7 is the lowest priority).
One of two methods can be used to move data from the IDP FIFO to
internal memory:
• The core can remove data from the FIFO manually by reading the
memory-mapped register,
IDP_FIFO. The output of the FIFO is
held in the (read-only)
IDP_FIFO register. When this register is
read, the corresponding element is removed from the IDP FIFO,
and the next element is moved into the
IDP_FIFO register.
To Next Page
Loading...
Need help?
General
