ADSP-21368 SHARC Processor Hardware Reference 6-27
Serial Peripheral Interface Ports
5. Configure DMA by writing to the DMA parameter registers and
the
SPIDMACx register.
DMA Chaining
For information about chaining, refer to “Setting Up and Starting
Chained DMA over the SPI” on page 2-42.
SPI Transfer Formats
The SPI ports support four different combinations of serial clock phases
and polarity. The application code can select any of these combinations
using the CLKPL and CPHASE bits in the SPICTL register.
Figure 6-5 on page 6-28 shows the transfer format when CPHASE = 0 and
Figure 6-6 on page 6-29 shows the transfer format when CPHASE = 1. Each
diagram shows two waveforms for SPICLK—one for CLKPL = 0 and the
other for CLKPL = 1. The diagrams may be interpreted as master or slave
timing diagrams since the SPICLK, MISO, and MOSI pins are directly con-
nected between the master and the slave. The MISO signal is the output
from the slave (slave transmission), and the MOSI signal is the output from
the master (master transmission).
The
SPICLK signal is generated by the master, and the SPIDS signal repre-
sents the slave device select input to the SPI slave from the SPI master.
The diagrams represent 8-bit transfers (
WL = 0) with MSB first (MSBF = 1).
Any combination of the
WL and MSBF bits of the SPICTL register is allowed.
For example, a 16-bit transfer with the LSB first is one possible
configuration.
The clock polarity and the clock phase should be identical for the master
and slave devices involved in the communication link. The transfer format
from the master may be changed between transfers to adjust to various
requirements of a slave device.
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