SPI Data Transfer Operations
6-26 ADSP-21368 SHARC Processor Hardware Reference
With disabling the SPI:
1. Disable the SPI port by writing 0x00 to the
SPICTLx registers.
2. Disable DMA and clear the FIFO by writing 0x80 to the SPIDMACx
registers. This ensures that any data from a previous DMA opera-
tion is cleared before configuring a new DMA operation.
3. Clear all errors by writing to the W1C-type bits (see Table A-11 on
page A-57) in the SPISTATx registers. This ensures that the error
bits SPIOVF and SPIUNF (in the SPIDMACx registers) are cleared when
a new DMA is configured.
4. Reconfigure the SPICTLx registers and enable SPI using the SPIEN
bit.
5. Configure DMA by writing to the DMA parameter registers and
the SPIDMACx registers.
Without disabling the SPI:
1. Disable DMA and clear the FIFO by writing 0x80 to the SPIDMAC
register. This ensures that any data from a previous DMA opera-
tion is cleared before configuring a new DMA operation.
2. Clear the RXSPIx/TXSPIx registers and the buffer status without dis-
abling the SPI. This can be done by ORing 0xC0000 with the
present value in the SPICTLx registers. Use the RXFLSH and TXFLSH
bits to clear the
RXSPIx/TXSPIx registers and the buffer status.
3. Clear all errors by writing to the W1C-type bits in the SPISTAT
register. This ensures that error bits SPIOVF and SPIUNF in the
SPIDMACx registers are cleared when a new DMA is configured.
4. Reconfigure
SPICTL to remove the clear condition of the
RXSPI/TXSPI register bits.
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