ADSP-21368 SHARC Processor Hardware Reference A-43
Register Reference
SPORT Transmit Buffer Registers (TXSPx)
The addresses of the TXSPx registers are:
The 32-bit
TXSPx registers hold the output data for serial port transmit
operations. The reset value for these registers is undefined. For more
information on how transmit buffers work, see “Transmit and Receive
Data Buffers (TXSPxA/B, RXSPxA/B)” on page 5-67.
22–16 CHNL Current Channel Selected (read-only, sticky). Identify the cur-
rently selected transmit channel slot (0 to 127).
23 MCEB Multichannel Enable, B Channels.
0 = Disable
1 = Enable
27–24 DMASxy DMA Status. Selects the transfer status.
0 = Inactive
1 = Active
(read-only)
31–28 DMACHSxy DMA Chaining Status.
0 = Inactive
1 = Active
(read-only)
TXSP0A – 0xC60 TXSP0B – 0xC62
TXSP1A – 0xC64 TXSP1B – 0xC66
TXSP2A – 0x460 TXSP2B – 0x462
TXSP3A – 0x464 TXSP3B – 0x466
TXSP4A – 0x860 TXSP4B – 0x862
TXSP5A – 0x864 TXSP5B – 0x866
TXSP6A – 0x4860 TXSP6B – 0x4862
TXSP7A – 0x4864 TXSP7B – 0x4866
Table A-9. SPMCTLx Register Bit Descriptions (Cont’d)
Bit Name Description
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