ADSP-21368 SHARC Processor Hardware Reference 5-35
Serial Ports
SPORT Loopback
When the SPORT loopback bit, SPL bit 12, is set in the SPMCTLx, control
registers, the SPORT is configured in an internal loopback connection as
follows: SPORT0 and SPORT1 work as a pair for internal loopback,
SPORT2 and SPORT3 work as pairs, SPORT4 and SPORT5 and
SPORT6 and SPORT7 work as pairs. The loopback mode enables pro-
grams to internally test the SPORTs and to debug applications.
When loopback is configured:
• SPORTx_DA, SPORTx_DB, SPORTx_CLK and SPORTx_FS signals of
SPORT0 and SPORT1 are internally connected (where x = 0 or 1).
• SPORTy_DA, SPORTy_DB, SPORTy_CLK, and SPORTy_FS signals of
SPORT2 and SPORT3 are internally connected (where y = 2 or 3).
• SPORTz_DA, SPORTz_DB, SPORTz_CLK and SPORTz_FS signals of
SPORT4 and SPORT5 are internally connected (where z = 4 or 5).
• SPORTn_DA, SPORTn_DB, SPORTn_CLK and SPORTn_FS signals of
SPORT6 and SPORT7 are internally connected (where n = 6 or
7).
In loopback mode, either of the two paired SPORTs can be transmitters
or receivers. One SPORT in the loopback pair must be configured as a
transmitter; the other must be configured as a receiver. For example,
SPORT0 can be a transmitter and SPORT1 can be a receiver for internal
loopback. Or, SPORT0 can be a receiver and SPORT1 can be the trans-
mitter when setting up internal loopback. The processor ignores external
activity on the SPORTx_CLK, SPORTx_FS A and B channel data signals when
the SPORT is configured in loopback mode which prevents contention
with the internal loopback data transfer.
L
Only transmit clock and transmit frame sync options may be used
in loopback mode—programs must ensure that the SPORT is set
up correctly in the
SPCTLx control registers. Multichannel mode is
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