Analog Devices SHARC ADSP-21368 User Manual

SPORT Operation Modes
5-34 ADSP-21368 SHARC Processor Hardware Reference
Programming Packed I
2
S Mode
Since packed I
2
S mode is implemented on top of TDM, programming
this modes is the same as programming TDM. Use the serial port control
(SPCTLx) and channel selection registers to configure the serial ports to run
in packed I
2
S mode as follows.
1. Set the
OPMODE bit (bit 11, = 1) in the SPCTLx register to configure
the processor to run in packed I
2
S mode.
2. Configure the ICLK (bit 10) and IFS (bit 14) bits to emulate I
2
S
master or slave which in this case is internal or external clock and
frame sync.
In the I
2
S standard, the master generates both clock and frame sync
and the slave uses external clock and frame sync.
3. Configure the channel select registers. See “Channel Selection Reg-
isters” on page 5-31.
4. Set the CKRE bit (bit 12) to 1 in both transmitter and receiver to
emulate I
2
S mode.
In the I
2
S standard, the transmitter drives output at the clock fall-
ing edge and the receiver samples the input at the clock rising edge.
This does not apply to packed I
2
S mode.
5. Clear (= 0) the LSBF bit in both transmitter and receiver to emulate
I
2
S mode. In the I
2
S standard, the MSB of a word is sent first. In
packed I
2
S mode, this is not the case.
6. To emulate I
2
S in packed I
2
S mode, set (=1) the MFD bit in the
SPMCTLx register. In TDM mode, the transmitter starts to transmit
the first bit of data immediately upon the frame sync pulsing high.
In the I
2
S standard, data transmission starts one cycle after the
frame sync pulse toggles.

Analog Devices SHARC ADSP-21368 Specifications

General

Brand	Analog Devices
Model	SHARC ADSP-21368
Category	Computer Hardware
Language	English