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ADSP-21368 SHARC Processor Hardware Reference 5-31

Serial Ports

This bit is set when the channel has received new data while the

RXSPxA or

RXSPxB buffer is full. New data then overwrites existing data. When the

SPORT is configured as a transmitter this bit indicates the transmit

underflow status (sticky, read-only). This bit is set, = 1 when multichannel

SPORTx_FS signal (from internal or external source) occurred while the

TXS buffer was empty.

Bits 31-30 and bits 28-27 (DXS_B) in the SPCTLx registers indicate the

buffer status of the channel A and B buffer contents as follows: 00 = buffer

empty, 01 = reserved, 10 = buffer partially full, 11 = buffer full.

Channel Selection Registers

Specific channels can be individually enabled or disabled to select the

words that are received and transmitted during multichannel communica-

tions. Data words from the enabled channels are received or transmitted,

while disabled channel words are ignored. Up to 128 channels are avail-

able for transmitting and receiving.

The multichannel selection registers enable and disable individual chan-

nels. The registers for each SPORT are shown in Table 5-2.

Table 5-2. Multichannel Selection Registers

SP1CS(0–3)

SP3CS(0–3)

SP5CS(0–3)

SP7CS(0–3)

SP0CS(0–3)

SP2CS(0–3)

SP4CS(0–3)

SP6CS(0–3)

Multichannel Active Channels Select. Specifies the active trans-

mit/receive channels (4x32-bit registers for 128 channels).

Analog Devices SHARC ADSP-21368 User Manual

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