SPORT Operation Modes
5-32 ADSP-21368 SHARC Processor Hardware Reference
Each of the four multichannel enable and compand select registers are 32
bits in length. These registers provide channel selection for 128 (32 bits x
4 channels = 128) channels. Setting a bit enables that channel so that the
SPORT selects its word from the multiple-word block of data (for either
receive or transmit). For example, setting bit 0 in
SP0CS0 or SP2CS0 selects
word 0, setting bit 12 selects word 12, and so on. Setting bit 0 in SP0CS1
or SP2CS1 selects word 32, setting bit 12 selects word 44, and so on.
Setting a particular bit to 1 in the SPxCS (0–3)registers causes the SPORTx
to transmit or receive the word in that channel’s position of the data
stream. Clearing the bit in the register causes the SPORTx_DA data transmit
signal to three-state during the time slot of that channel if the SPORT is
configured as transmitter. If the SPORT is configured as receiver, the data
received is ignored.
Companding may be selected on a per-channel basis. Setting a bit to 1 in
any of the multichannel registers specifies that the data be companded for
that channel. A-law or μ-law companding can be selected using the
DTYPE
bit in the
SPCTLx control registers. SPORT1, 3, 5 and 7 expand selected
incoming time slot data, while SPORT0, 2, 4 and 6 can compand the
data.
SP1CCS(0–3)
SP3CCS(0–3)
SP5CCS(0–3)
SP7CCS(0–3)
Multichannel Receive Compand Select. Specifies which active receive
channels (out of 128 channels) are companded.
SP0CCS(0–3)
SP2CCS(0–3)
SP4CCS(0–3)
SP6CCS(0–3)
Multichannel Transmit Compand Select. Specifies which active trans-
mit channels (out of 128 channels) are companded.
Table 5-2. Multichannel Selection Registers (Cont’d)
Register Names Function
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