Conditioning Input Signals
14-32 ADSP-21368 SHARC Processor Hardware Reference
Input Synchronization Delay
The processor has several asynchronous inputs—RESET, TRST, IRQ2–0,
MS3–0, and FLAG16-0 (when configured as inputs). These inputs can be
asserted in arbitrary phase to the processor clock, CLKIN. The processor
synchronizes the inputs prior to recognizing them. The delay associated
with recognition is called the synchronization delay.
Any asynchronous input must be valid prior to the recognition point in a
particular cycle. If an input does not meet the setup time on a given cycle,
it may be recognized in the current cycle or during the next cycle.
To ensure recognition of an asynchronous input, it must be asserted for at
least one full processor cycle plus setup and hold time, except for RESET,
which must be asserted for at least four processor cycles. The minimum
time prior to recognition (the setup and hold time) is specified in the pro-
cessor’s data sheet.
Conditioning Input Signals
The processor is a CMOS device. It has input conditioning circuits which
simplify system design by filtering or latching input signals to reduce sus-
ceptibility to glitches or reflections.
The following sections describe why these circuits are needed and their
effect on input signals.
A typical CMOS input consists of an inverter with specific N and P device
sizes that cause a switching point of approximately 1.4 V. This level is
selected to be the midpoint of the standard TTL interface specification of
V
IL
= 0.8 V and V
IH
= 2.0 V. This input inverter, unfortunately, has a fast
response to input signals and external glitches wider than 1 ns. Filter cir-
cuits and hysteresis are added after the input inverter on some processor
inputs, as described in the following sections.
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