Data Transfer Mechanics
12-10 ADSP-21368 SHARC Processor Hardware Reference
16-Bit Receive FIFO Register
The TWI 16- bit FIFO receive register (RXTWI16) holds a 16-bit data value
read from the FIFO buffer. Although peripheral bus reads are 32 bits, a
read access to the RXTWI16 register can only access two receive data bytes
from the FIFO buffer. To reduce interrupt output rates and peripheral
bus access times, a double-byte receive data access can be performed. Two
data bytes can be read, effectively emptying the receive FIFO buffer with a
single access.
The data is read in little-endian byte order, as shown in Figure 12-2 on
page 12-9, where byte 0 is the first byte received and byte 1 is the second
byte received. With each access, the receive status (TWIRXS) field in the
TWIFIFOSTAT register is updated to indicate it is empty. If an access is per-
formed while the FIFO buffer is not full, the core waits until the receive
FIFO buffer is full and then completes the read access. All bits in this reg-
ister are write-only. For more information, see “16-Bit Receive FIFO
Register (RXTWI16)” on page A-154.
Data Transfer Mechanics
The TWI controller follows the transfer protocol of the Philips I
2
C Bus
Specification version 2.1 dated January 2000. A simple complete transfer is
diagrammed in Figure 12-3.
Figure 12-3. Basic Data Transfer
7-BIT ADDRESS 8-BIT DATAR/W ACK PACKS
S = START
P = STOP
ACK = ACKNOWLEDGE
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