ADSP-21368 SHARC Processor Hardware Reference 5-69
Serial Ports
To support debugging buffer transfers, the ADSP-21367/8/9 and
ADSP-2137x processors have a buffer hang disable (
BHD) bit. When set
(= 1), this bit prevents the processor core from detecting a buffer-related
stall condition, permitting debugging of this type of stall condition. For
more information, see the BHD bit description on on page 5-64.
The status bits in SPCTLx are updated during reads and writes from the
core processor even when the SPORT is disabled. Disable the SPORT
when writing to the receive buffer or reading from the transmit buffer.
L
When programming the SPORT channel (A or B) as a transmitter,
only the corresponding TXSPxA and TXSPxB buffers become active
while the receive buffers RXSPxA and RXSPxB remain inactive. Simi-
larly, when the SPORT channel A and B are programmed as
receive-only, the corresponding RXSPxA and RXSPxB are activated.
Do not attempt to read or write to inactive data buffers. If the pro-
cessor operates on the inactive transmit or receive buffers while the
SPORT is enabled, unpredictable results may occur.
Clock and Frame Sync Frequency Registers (DIVx)
The DIVx registers contain divisor values that determine frequencies for
internally-generated clocks and frame syncs. The DIVx registers are
described in Appendix A in “SPORT Divisor Registers (DIVx)” on
page A-44 and are shown in Figure 5-10.
The CLKDIV bit field specifies how many times the processor’s internal
clock (CCLK) is divided to generate the transmit and receive clocks. The
frame sync (
SPORTx_FS) is considered a receive frame sync if the data sig-
nals are configured as receivers. Likewise, the frame sync SPORTx_FS is
considered a transmit frame sync if the data signals are configured as
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