SPORT Control Registers and Data Buffers
5-68 ADSP-21368 SHARC Processor Hardware Reference
buffer is ready to accept the next word (for example, the transmit buffer is
not full). This interrupt does not occur when SPORT DMA is enabled or
when the corresponding mask bit in the
LIRPTL/IRPTL register is set.
When the SPORT is configured as a transmitter (SPTRAN =1) and a trans-
mit frame sync occurs and no new data has been loaded into the transmit
buffer, a transmit underflow status bit is set in the SPORT control regis-
ters. The TUVF_A/ROVF_A or TUVF_A status bit is sticky and is only cleared
by disabling the SPORT.
When the SPORT is configured as a receiver (SPTRAN = 0), the receive
buffers are activated. The receive buffers act like a three-location FIFO
because they have two data registers plus an input shift register. Two com-
plete 32-bit words can be stored in the receive buffer while a third word is
shifted in. The third word overwrites the second if the first word has not
been read out (by the processor core or the DMA controller). When this
happens, the receive overflow status bit is set in the SPORT control regis-
ters. Almost three complete words can be received without the receive
buffer being read before an overflow occurs. The overflow status is gener-
ated on the last bit of the third word. The ROVF_A/ROVF_A or TUVF_A status
bit is sticky and is cleared only by disabling the SPORT.
An interrupt is generated when the receive buffer is loaded with a received
word (for example, the receive buffer is not empty). This interrupt is
masked if SPORT DMA is enabled or if the corresponding bit in the
LIRPTL register is set.
If your program causes the core processor to attempt to read from an
empty receive buffer or to write to a full transmit buffer, the access is
delayed until the buffer is accessed by the external I/O device. This delay
is called a core processor hang. In order to access the receive or transmit
buffer without a hang, read the buffer’s status to determine whether the
access can be made.
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