ADSP-21368 SHARC Processor Hardware Reference 13-5
Precision Clock Generators
Frame sync generation from a unit is independently enabled and con-
trolled. Sources for the frame sync generation can be either from the
crystal buffer output,
PCLK, or an external pin source. There is only one
external source pin for both frame sync and clock output for a unit. If an
external source is selected for both frame sync and clock output for a unit,
then they operate on the same input signal. Apart from enable and source
select control bits, frame sync generation is controlled by a 20-bit divisor,
a 16-bit pulse width control, and a 20-bit phase control.
There are two modes of operation for the PCG frame sync. The divisor
field determines if the frame sync operates in normal mode
(divisor > 1) or bypass mode (divisor = 0 or 1).
Normal Mode
In normal mode, the frequency of the frame sync output is determined by
the divisor where:
The high period of the frame sync output is controlled by the value of the
pulse width control. The value of the pulse width control should be less
than the value of the divisor.
The phase of the frame sync output is determined by the value of the
phase control. If the phase is zero, then the positive edges of the clock and
frame sync coincide, provided the divisors of the clock and frame sync are
the same, the source for the clock and frame sync is also the same, and if
clock and frame sync are enabled at the same time using a single
instruction.
The number of input clock cycles that have already elapsed before the
frame sync is enabled is equal to the difference between the divisor and the
phase values. If the phase is a small fraction of the divisor, then the frame
Frequency of Clock Input
Frame Sync Divisor
Frequency of Frame Sync Output =
(
)
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