Parallel Data Acquisition Port (PDAP)
7-12 ADSP-21368 SHARC Processor Hardware Reference
Clocking Edge Selection
Notice that in all four packing modes described, data is read on a clock
edge, but the specific edge used (rising or falling) is not indicated. Clock
edge selection is configured using the IDP_PDAP_CLKEDGE bit (bit 29 of the
IDP_PP_CTL register). Setting this bit (= 1) causes the data to latch on the
falling edge. Clearing this bit (= 0) causes data to latch on the rising edge
(default).
Hold Input
A synchronous clock enable signal can be passed from any DAI pin to the
PDAP packing unit. This signal is called PDAP_HOLD.
L
The PDAP_HOLD signal is actually the same physical internal signal as
the frame sync for IDP channel 0. Its functionality is determined
by the PDAP enable bit (IDP_PDAP_EN).
When the PDAP_HOLD signal is HIGH, all latching clock edges are ignored
and no new data is read from the input pins. The packing unit operates as
normal, but it pauses and waits for the PDAP_HOLD signal to be deasserted
and waits for the correct number of distinct input samples before passing
the packed data to the FIFO.
Figure 7-14 shows the affect of the hold input (B) for four 8-bit words in
packing mode 00, and Figure 7-15 shows the affect of the hold input (B)
for two 16-bit words in packing mode 10.
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