ADSP-21368 SHARC Processor Hardware Reference 14-39
System Design
External Port Booting
The ADSP-21367/8/9 processors allow booting through the external port.
There are two options, which are described in the following sections.
Booting Through the AMI
The asynchronous memory interface (AMI) supports an 8-bit user boot
called AMI boot. Only the
MS1 signal is used for AMI(FLASH/EEPROM)
booting. Table 14-10 shows the bit settings for AMI boot. These bits are
described in detail in “AMI Control Registers (AMICTLx)” on page A-17.
Table 14-10. AMI Boot Bit Settings (AMICTLx)
Bit Setting
AMI Enable (AMIEN) 1
Bus Width (BW) 00
Packing Disabled (PKDIS) 0
Most Significant Word First (MSWF) 0
ACK Pin Enable (ACKEN) 0
Wait States (WS) 10111
Bus Hold Cycle at the End of Write Access (HC) 000
Idle Cycle (IC) 000
Buffer Flush (FLSH) 0
Read Hold Cycle at the End of Read Access (RHC) 000
Disable Predictive Reads (NO_OPT) 0
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