Interrupt Registers
B-22 ADSP-21368 SHARC Processor Hardware Reference
Interrupt Mask Pointer Register (IMASKP)
The IMASKP register is a non-memory-mapped, universal, system register
(Ureg and Sreg). The reset value for this register is 0x0000 0000. Each bit
in the IMASKP register corresponds to a bit with the same name in the
IRPTL registers. The IMASKP register field descriptions are shown in
Figure B-3 and Figure B-4 and described in Table B-7.
This register supports an interrupt nesting scheme that lets higher priority
events interrupt an interrupt service routine (ISR) and keeps lower prior-
ity events from interrupting.
When interrupt nesting is enabled, the bits in the IMASKP register mask
interrupts with lower priorities than the interrupt that is currently being
serviced. Other bits in this register unmask interrupts having higher prior-
ity than the interrupt that is currently being serviced. Interrupt nesting is
enabled using NESTM in the MODE1 register. The IRPTL register latches a
lower priority interrupt even when masked, and the processor responds to
that latched interrupt if it is later unmasked.
When interrupt nesting is disabled (NESTM = 0 in the MODE1 register), the
bits in the IMASKP register mask all interrupts while an interrupt is cur-
rently being serviced. The IRPTL register still latches these interrupts even
when masked, and the processor responds to the highest priority latched
interrupt after servicing the current interrupt.
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