Interrupt Registers
B-14 ADSP-21368 SHARC Processor Hardware Reference
The interrupt latch bits 11 through 19 are programmable through the
programmable interrupt controller register (PICR). The descriptions pro-
vided are their default sources. For information on their optional use, see
“Peripheral Interrupt Priority Control Registers” on page A-164.
Figure B-4. IRPTL, IMASK, and IMASKP Registers (Bits 15–0)
Table B-5. Interrupt Latch (IRPTL) Register Bit Descriptions
Bit Name Description
0EMUIEmulator Interrupt. Indicates if an EMUI is latched and is pending
(if set, = 1,) or no EMUI is pending (if cleared, = 0). An EMUI
occurs on reset and when an external device asserts the EMU
pin.
1RSTIReset Interrupt. Indicates if an RSTI is latched and is pending
(if set, = 1), or no RSTI is pending (if cleared, = 0). An RSTI occurs
on reset as an external device asserts the RESET
pin.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
Reserved
SOVFI
EMUI
P4I
Programmable Interrupt 4
(SPORT 3 Interrupt 0x3C)
Stack Full/Overflow (0x0C)
Reset (Reset 0x04)
IICDI
Emulator Interrupt
(Interrupt Vector Address
0x00)
P3I
Programmable Interrupt 3 (SPORT
1 Interrupt 0x38)
P2I
Programmable Interrupt 2 (Gen-
eral-Purpose IOP Timer 0
Interrupt 0x34)
P1I
Programmable Interrupt 1
(SPI Transmit or Receive High Priority
Interrupt 0x30)
P0I
Programmable Interrupt 0
(DAI1 Interrupt 0x2C)
IRQ0I
IRQ0_I Hardware Interrupt (0x28)
IRQ1_I Hardware Interrupt (0x24)
IRQ1I
RSTI
Illegal Input Condition
Detected (0x08)
TMZHI
Timer Expired
High Priority (0x10)
SPERRI
Hardware Breakpoint
Interrupt (0x18)
IRQ2_I Hardware Interrupt (0x20)
IRQ2I
BKPI
IRPTL (Bits 15-0)
Defaults in parenthesis
SP Error Interrupt
Interrupt (0x18)
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