ADSP-21368 SHARC Processor Hardware Reference B-15
Interrupts
2IICDIIllegal Input Condition Detected Interrupt. Indicates if an IICDI is
latched and is pending (if set, = 1), or no IICDI is pending
(if cleared, = 0). An IICDI occurs when a true results from the logical
Oring of the illegal I/O processor register access (IIRA) and unaligned
64-bit memory access bits in the STKYx registers.
3SOVFIStack Overflow/Full Interrupt. Indicates if a SOVFI is latched and is
pending (if set, = 1), or no SOVFI is pending (if cleared, = 0). An
SOVFI occurs when a stack in the program sequencer overflows or is
full.
4TMZHITimer Expired High Priority. Indicates if a TMZHI is latched and is
pending (if set, = 1), or TMZHI is not pending (if cleared, = 0). A
TMZHI occurs when the timer decrements to zero. Note that this
event also triggers a TMZLI. The timer operations are controlled as
follows:
• The TCOUNT register contains the timer counter. The
timer decrements the TCOUNT register each clock cycle.
• The TPERIOD value specifies the frequency of timer inter-
rupts. The number of cycles between interrupts is TPE-
RIOD + 1. The maximum value of TPERIOD is 2
32
– 1.
• The TIMEN bit in the MODE2 register starts and stops the
timer.
Since the timer expired event (TCOUNT decrements to zero) gener-
ates two interrupts, TMZHI and TMZLI, programs should unmask
the timer interrupt with the desired priority and leave the other one
masked.
5SPERRISP Error Interrupt.
6BKPIHardware Breakpoint Interrupt. Indicates if an BKPI is latched and
is pending (if set, = 1), or no BKPI is pending (if cleared, = 0).
7 Reserved
8IRQ2
I IRQ2 Hardware Interrupt. Indicates if an IRQ2I is latched and is
pending (if set, = 1), or no IRQ2I is pending (if cleared, = 0). An
IRQ2I occurs when an external device asserts the FLAG2 pin config-
ured as IRQ2
.
Table B-5. Interrupt Latch (IRPTL) Register Bit Descriptions (Cont’d)
Bit Name Description
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