SPORT Operation Modes
5-10 ADSP-21368 SHARC Processor Hardware Reference
(
SPORTx_CLK_O) to the pin buffer input (PBxx_I). The connection of
PBxx_O to SPORTx_CLK_I opens a vulnerability to a glitch coming in even
though the SPORT is driving the clock as an output. By programming
SRU1 to remove this input path, programs can avoid this vulnerability.
This is done by leaving the routing of SPORTx_CLK_O to PBxx_I as before,
providing the SPORT clock off chip, but also routing it directly back to
SPORTx_CLK_I to give the state machine its signal. This effectively closes
off the external access to SPORTx_CLK_I. In the SRU programming code,
the following code should be added: SRU(SPORTx_CLK_O,SPORTx_CLK_I).
For more information, see Chapter 4, Digital Audio/Digital Peripheral
Interfaces.
SPORT Operation Modes
SPORTs operate in four modes:
• Standard DSP serial mode, described in “Standard DSP Serial
Mode” on page 5-12
• Left-justified sample pair mode, described in “Left-Justified Sam-
ple Pair Mode” on page 5-16
•I
2
S mode, described in “I2S Mode” on page 5-20
• Multichannel mode, described in “Multichannel Operation” on
page 5-25
L
Bit names and their functions change based on the SPORT operat-
ing mode. See the mode specific section for the bit names and their
functionality.
The SPORT operating mode can be selected via the SPCTLx register. See
Table 5-1 for a summary of the control bits as they relate to the four oper-
ating modes.
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