Analog Devices SHARC ADSP-21368 User Manual

Sony/Philips Digital Interface Registers
A-94 ADSP-21368 SHARC Processor Hardware Reference
Receiver Status Register (DIRSTAT)
This 32-bit, read-only register is used to store the error bits. The error bits
are sticky on read. Once they are set, they remain set until the register is
read. This register also contains the lower byte of the 40-bit channel status
information. The register is located at address 0x24A9. The register’s bits
are shown in Figure A-35 and described in Table A-39.
Figure A-35. DIRSTAT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0000000000000000
DIR_NOAUDIOL
DIR_BIPHASEERROR
Biphase Error
0=No biphase error
1=Biphase error
Non-Audio Subframe Mode
Channel 1
0=Not non-audio subframe
mode
1=Non-audio subframe mode,
channel 1
DIRSTAT (0x24A9)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
DIR_B0CHANL
Reserved
DIR_VALID
Validity Bit. ORed Value of Channel 1 and 2
0=Linear PCM data
1=Non-linear audio data
DIR_PARITYERROR
Parity Bit. Indicates Parity Error
0=No parity error
1=Parity error
DIR_NOSTREAM
Stream Disconnected
0=Stream not disconnected
1=Stream disconnected
DIR_LOCK
Lock Receiver
0=Receiver not locked
1=Receiver locked
DIR_NOAUDIOR
Non-Audio Subframe Mode
Channel 2
0=Not non-audio subframe
mode
1=Non-audio subframe mode,
channel 2
DIR_NOAUDIOLR
Non-Audio Subframe Mode
Channel 1 and 2
0=Not non-audio frame mode
1=Non audio frame mode
DIR_B0CHANR
Channel Status Byte 0 for
Subframe A
Channel Status Byte 0 for Subframe B

Analog Devices SHARC ADSP-21368 Specifications

General

Brand	Analog Devices
Model	SHARC ADSP-21368
Category	Computer Hardware
Language	English