SDRAM Controller
3-70 ADSP-21368 SHARC Processor Hardware Reference
Auto-Refresh
The SDRAM internally increments the refresh address counter and causes
a CAS before RAS (CBR) refresh to occur internally for that address when
the auto-refresh command is given. The SDC generates an auto-refresh
command after the SDC refresh counter times out. The
RDIV value in the
SDRAM refresh rate control register (SDRRC) must be set so that all
addresses are refreshed within the t
REF
period specified in the SDRAM
timing specifications.
Before executing the auto-refresh command, the SDC executes a pre-
charge all command to all external banks. The next activate command is
not given until the t
RFC
specification (t
RFC
= t
RAS
+ t
RP
) is met.
Auto-refresh commands are also issued by the SDC as part of the
power-up sequence and after exiting self-refresh mode.
Self-Refresh Mode
This mode causes refresh operations to be performed internally by the
SDRAM, without any external control. This means that the SDC does not
generate any auto-refresh cycles while the SDRAM is in self-refresh mode.
Self-refresh entry—Self-refresh mode is enabled by writing a 1 to the
SDSRF bit of the SDRAM memory control register (SDCTL). This de-asserts
the SDCKE pin and puts the SDRAM in self-refresh mode if no access is
currently underway. The SDRAM remains in self-refresh mode for at least
t
RAS
and until an internal access (read/write) to SDRAM space occurs
Self-refresh exit—When any SDRAM access occurs, the SDC asserts
SDCKE high which causes the SDRAM to exit from self-refresh mode. The
SDC waits to meet the t
XSR
specification (t
XSR
= t
RAS
+ t
RP
) and then
issues an auto-refresh command. After the auto-refresh command, the
SDC waits for the t
RFC
specification (t
RFC
= t
RAS
+ t
RP
) to be met before
executing the activate command for the transfer that caused the SDRAM
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