ADSP-21368 SHARC Processor Hardware Reference 14-9
System Design
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When the SPIPDN bit (bit 30 in the PMCTL register) is set (= 1 which
shuts down the clock to the SPI), the FLAGx pins cannot be used
(through the FLAGS7–0 register bits) because the FLAGx pins are syn-
chronized with the clock.
Programming Flags
There are 16 system flags and they can be programmed using the FLAGS
register shown in Figure 14-3. Only four flags are connected to
FLAG/IRQ0-3 pins after reset. If more flags are required, they can be pro-
grammed in the DATA pins (using the SYSCTL register, see Table A-1 on
page A-6) or they can be programmed with the SRU2 pins (using SRU2
registers, see “DPI/SRU2 Connection Groups” on page 4-51).
The FLAGS register consists of two bits for each flag, one bit to specify flag
direction (or output select) where 0 = input, 1 = output and the other bit
to specify the flag’s value. If flags are in input mode, the flag value in
FLAGS register is read-only and it shows the input flag status. If flags are in
output mode, then the flag value can be written to change output flags
and it can also be read to determine the last value written.
FLAGS can be mapped into any of the following three pin groups:
1. Four FLAG/IRQ pins
• Only
FLAG0–3 can be mapped.
• Should be programmed through
SYSCTL register according
to
EPDATA mode, IRQxEN, TMREXPEN, and MSEN.
• IRQEN and TMREXPEN take priority over all other modes of
these pins.
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