Setting Up DMA Parameter Registers
2-26 ADSP-21368 SHARC Processor Hardware Reference
• Serial port transmit buffers (
TXSPx). These transmit buffers for the
serial ports have two-position FIFOs for transmitting data when
connected to another serial device.
• SPI receive buffers (RXSPI, RXSPIB). These receive buffers for the
SPI ports have a single-position buffer for receiving data when con-
nected to another serial device.
• SPI transmit buffers (TXSPI, TXSPIB). These transmit buffers for
the SPI ports have a single-position buffer for transmitting data
when connected to another serial device.
• Input data port buffers (IDP_FIFO). This receive buffer for the
input data port has eight-position buffers for receiving data when
connected to another device.
Port, Buffer, and DMA Control Registers
The port, buffer, and DMA control registers in Figure 2-2 shows the con-
trol registers for the ports and DMA channels. These registers include:
• External port control registers (DMACx). These are the control regis-
ters for the external port DMA channels.
• Input data port control register (IDP_CTL). This is the control reg-
ister for the input data ports.
• Serial port control registers (
SPCTLx, SPMCTLx). These control reg-
isters select the receive or transmit format, monitor FIFO status,
enable chaining, and start DMA for each serial port.
• SPI port control registers (
SPICTL, SPICTLB). These control regis-
ters configure and enable the two SPI interfaces, selecting the
devices as masters or slaves, and determine the data transfer and
word size. The SPIDMAC and SPIDMACB registers also control SPI
DMA and FIFO status.
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