ADSP-21368 SHARC Processor Hardware Reference 2-27
I/O Processor
• Universal asynchronous receiver/transmitter registers
(
RXCTL_UACx, TXCTL_UACx). These control registers configure and
enable the UART receiver and transmitter DMA, (chaining and
non chaining).
• Memory-to-memory DMA control register (MTMCTL). This control
register contains the MTM DMA read and write channel enable
and status bits.
Table 2-6 shows the parameter registers for each DMA channel. These
registers function similarly to data address generator registers and include:
• Internal index registers (IISPx, IISPI, IISPIB, IIEP, IDP_DMA_Ix,
RXI_UAC/TXI_UAC). Index registers provide an internal memory
address, acting as a pointer to the next internal memory DMA read
or write location.
• Internal modify registers (IMSPx, IMEP, IMSPI, IMSPIB, IDP_DMA_Mx,
RXM_UAC/TXM_UAC). Modify registers provide the signed increment
by which the DMA controller post-modifies the corresponding
internal memory index register after the DMA read or write.
• Count registers (CSPx, ICEP, CSPI, CSPIB, IDP_DMA_Cx,
RXC_UAC/TXC_UAC). Count registers indicate the number of words
remaining to be transferred to or from internal memory on the cor-
responding DMA channel.
• Chain pointer registers (
CPSPx, CPSPI, CPSPIB, CPEP,
RXCP_UAC/TXCP_UAC). Chain pointer registers hold the starting
address of the TCB (parameter register values) for the next DMA
operation on the corresponding channel. These registers also con-
trol whether the I/O processor generates an interrupt when the
current DMA process ends.
• External index registers (
EIEPx). Index registers provide an exter-
nal memory address, acting as a pointer to the next external
memory DMA read or write location.
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