ADSP-21368 SHARC Processor Hardware Reference 7-3
Input Data Port
The IDP’s DMA engine implements DMA for all eight channels. Each of
the eight channels has a set of DMA parameter registers for directing the
data to memory location.
The following sections describe each of the input data port functions.
Serial Inputs
The IDP provides up to eight serial input channels—each with its own
clock, frame sync, and data inputs. The eight channels are automatically
multiplexed into a single 32-bit by eight-deep FIFO. Data is always for-
matted as a 64-bit frame and divided into two 32-bit words. The serial
protocol is designed to receive audio channels in I
2
S, left-justified sample
pair, or right-justified mode. One frame sync cycle indicates one 64-bit
left/right pair, but data is sent to the FIFO as 32-bit words (that is,
one-half of a frame at a time). The processor supports 24- and 32-bit I
2
S,
24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justified
formats.
Figure 7-2. Detail of IDP Channel 0
PDAP ENABLE
DAI PINS
[20:1]
DATA
[31:12]
[19:0]
20
20
PACKING
UNIT
SERIAL
INPUT
29
32
32
TO
FIFO
PARALLEL DATA ACQUISITION PORT
To Next Page
Loading...
Need help?
General
