Serial Inputs
7-4 ADSP-21368 SHARC Processor Hardware Reference
An audio signal that is normally 24 bits wide is contained within the
32-bit word. Four more bits are available for status and formatting data
(compliant with the IEC 90958, S/PDIF, and AES3 standards). An addi-
tional bit identifies the left/right one-half of the frame. If the data is not in
IEC standard format, the serial data can be any data word up to 28 bits
wide. Regardless of mode, bit 3 always specifies whether the data is
received in the first half (left channel) or the second half (right channel) of
the same frame, as shown in Figure 7-3. The remaining three bits are used
to encode one of the eight channels being passed through the FIFO to the
core. The FIFO output may feed eight DMA channels, where the appro-
priate DMA channel (corresponding to the channel number) is selected
automatically.
Note that each input channel has its own clock and frame sync input, so
unused IDP channels do not produce data and therefore have no impact
on FIFO throughput. The clock and frame sync of any unused input
should be assigned to low to avoid unintentional acquisition. The input
data port supports a maximum clock speed of 41.6 MHz.
The framing format is selected by using the IDP_SMODEx bits (three bits per
channel) in the IDP_CTL0 register. The bits (31–8) of the IDP_CTL0 register
control the input format modes for each of the eight channels. The eight
groups of three bits indicate the mode of the serial input for each of the
eight IDP channels, as shown in Table 7-1.
Figure 7-4 through Figure 7-9 show the FIFO data packing for the differ-
ent serial modes.
Figure 7-3. Word Format
31
87
432 0
AUDIO DATA (24 BITS)
AUDIO STREAM
STATUS
L/R
IDP
CHNL
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