Analog Devices SHARC ADSP-21368 - Page 423

ADSP-21368 SHARC Processor Hardware Reference 7-5
Input Data Port
Table 7-1. Serial Modes
Bit Field Values
IDP_SMODEx
Mode
000 Left-justified sample pair
001 I
2
S
010 Left-justified 32 bits. This is a single data and not a left/right
channel pair. It can be read as 32-bit data.
011 I
2
S-32 bit. This is a single data and not a left/right channel
pair. It can be read as 32-bit data.
100 Right-justified sample pair 24 bits
101 Right-justified sample pair 20 bits
110 Right-justified sample pair 18 bits
111 Right-justified sample pair 16 bits
Figure 7-4. FIFO Data Packing for I
2
S and Left-Justified
Figure 7-5. FIFO Data Packing for Right-Justified
Channel
Encoding
Bits (2–0)
L/R Encoding
Block Status
Channel
User Data
Validity
24-Bit
Audio
Data (31–8)
34567
Status
Channel
Encoding
Bits (2–0)
L/R Encoding
Spare Bits (7–4)
24-Bit
Audio
Data (31–8)
3
Set to LOW