Analog Devices SHARC ADSP-21368 User Manual

ADSP-21368 SHARC Processor Hardware Reference 2-25
I/O Processor
Data Buffer Registers
Figure 2-2 shows the data buffer registers for each port. These registers
include:
• Serial port receive buffers (RXSPx). These receive buffers for the
serial ports have two-position FIFOs for receiving data when con-
nected to another serial device.
Figure 2-2. I/O Processor Block Diagram
IDP
IDP FIFO
8DEEP
EXTERNEL
PORT
EXTERNAL
ADDRESS
GENERATOR
TXSP5A-0A,
TXSP5B-0B,
RXSP5A-0A,
RXSP5B-0B
(2 DEEP)
SPORTS
SPI PORT
RXSPI, TXSPI
(1 DEEP EACH)
SPI
DMA
FIFO
(4 DEEP)
IOD BUS
IISPI, IM S PI,
CSPI, CPSPI
SPI
IISP7A -0A,
IISP7B -0B,
IMSP7A-0A,
IM S P 7B-0B
CSP7A-0A,
CSP7B-0B,
CPSP7A-0A,
CPSP7B-0B
SPORT
IOA BUS
INTERNAL
DMA
PRIORITIZER
DMD, PMD
BUSES (TO CO R E)
I/O PROCESSOR
IDP_DMA_Ix
IDP_DMA_Mx
IDP_DMA_Cx
IDP
MUX
MUX
UART
UARTxRXCTL, IIUARTxRX
IMUARTxRX, CUARTxRX
CPUARTxRX, UARTxRXSTAT
UARTxTXCTL, IIUARTxTX
IMUARTxTX, CUARTxTX
CPUARTxTX, UARTxTXSTAT
EXTERNAL
PORT
EIEPx, EMEPx
ECEPx, IIEPx
IMEPx, ICEPx
CEPx, CPEPx
EBEPx, TPEPx
ELEPx
DFEP0 (DATA FIFO)
TFEP0 (TAP LIST FIFO)

Analog Devices SHARC ADSP-21368 Specifications

General

Brand	Analog Devices
Model	SHARC ADSP-21368
Category	Computer Hardware
Language	English