SPORT Control Registers and Data Buffers
5-72 ADSP-21368 SHARC Processor Hardware Reference
A software reset of the
SPEN_A or SPEN_B enable bit disables the SPORT(s)
and aborts any ongoing operations. Status bits are also cleared. The
SPORTs are ready to start transmitting or receiving data two serial clock
cycles after they are enabled in the SPCTLx registers. No serial clocks are
lost from this point on.
A hardware reset (RESET) disables the entire processor, including the
SPORTs, by clearing the SPCTLx registers. Any ongoing operations are
aborted.
SPORT Interrupts
Each SPORT has an interrupt associated with it. For each SPORT, both
the A and B channel transmit and receive data buffers share the same
interrupt vector. The interrupts can be used to indicate the completion of
the transfer of a block of serial data when the SPORTs are configured for
DMA. They can also be used to perform single word transfers (refer to
“Single Word Transfers” on page 5-81). The priority of the SPORT inter-
rupts is shown in Table 5-10.
Table 5-10. Priority of the Serial Port Interrupts
Interrupt Name
1
1 The interrupt names are defined in the def21367.h file supplied with the ADSP-21xxx DSP
development software.
Interrupt
SP1I SPORT1 DMA Channels (Highest Priority)
SP3I SPORT3 DMA Channels
SP5I SPORT5 DMA Channels
SP0I SPORT0 DMA Channels
SP2I SPORT2 DMA Channels
SP4I SPORT4 DMA Channels
SP6I SPORT6 DMA Channels
SP7I SPORT7 DMA Channels
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