ADSP-21368 SHARC Processor Hardware Reference 3-71
External Port
to exit self-refresh mode. Therefore, the latency from when a transfer is
received by the SDC while in self-refresh mode, until the activate com-
mand occurs for that transfer, is 2 × (t
RC
+ t
RP
) cycles
System clock during self-refresh mode. Note that the SDCLK is not dis-
abled by the SDC during self-refresh mode. However, software may
disable the clocks by clearing the DSDCTL bit in the SDCTL register. Pro-
grams should ensure that all applicable clock timing specifications are met
before the transfer to SDRAM address space (which causes the controller
to exit the self-refresh mode). If a transfer occurs to SDRAM address space
when the DSDCTL bit is cleared, an internal bus error is generated, and the
access does not occur externally, leaving the SDRAM in self-refresh mode.
The following steps are required when using self-refresh mode.
1. Set the SDSRF bit to enter self-refresh mode
2. Poll the SDSRA bit in the SDRAM status register (SDSTAT) to deter-
mine if the SDRAM has already entered self-refresh mode.
3. Optionally: set the DSDCTL bit to freeze SDCLK
4. Optionally: clear the DSDCTL bit to re-enable SDCLK
5. SDRAM access occurs the SDRAM exits from self-refresh mode
L
The minimum time between a subsequent self-refresh entry and
exit command is the t
RAS
cycle. If a self-refresh request is issued
during any external port DMA, the SDC grants the request with
the t
RAS
cycle and continues DMA operation afterwards.
No Operation/Command Inhibit
The no operation (NOP) command to the SDRAM has no effect on opera-
tions currently in progress. The command inhibit command is the same as
a NOP command; however, the SDRAM is not chip-selected. When the
SDC is actively accessing the SDRAM but needs to insert additional
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