ADSP-21368 SHARC Processor Hardware Reference 5-45
Serial Ports
Transmitting or receiving words smaller than 5 bits may cause incorrect
operation when all the DMA channels are enabled with no DMA
chaining.
Endian Format
Endian format determines whether serial words transmit MSB first or LSB
first. Endian format is selected by the
LSBF bit in the SPCTLx control regis-
ters. When
LSBF = 0, serial words transmit (or receive) MSB first. When
LSBF = 1, serial words transmit (or receive) LSB first.
Data Packing and Unpacking
Received data words of 16 bits or less may be packed into 32-bit words,
and 32-bit words being transmitted may be unpacked into 16-bit words.
Word packing and unpacking is selected by the PACK bit in the SPCTLx
control registers.
When PACK = 1 in the control registers, two successive words received are
packed into a single 32-bit word, and each 32-bit word is unpacked and
transmitted as two 16-bit words.
The first 16-bit (or smaller) word is right-justified in bits 15–0 of the
packed word, and the second 16-bit (or smaller) word is right-justified in
bits 31–16. This applies to both receive (packing) and transmit (unpack-
ing) operations. Companding can be used when word packing or
unpacking is being used.
When SPORT data packing is enabled, the transmit and receive interrupts
are generated for the 32-bit packed words, not for each 16-bit word.
L
When 16-bit received data is packed into 32-bit words and stored
in normal word space in processor internal memory, the 16-bit
words can be read or written with short word space addresses.
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