Analog Devices SHARC ADSP-21368 - Page 224

Making Connections in the SRUs
4-22 ADSP-21368 SHARC Processor Hardware Reference
Figure 4-15. SRU_CLK3 Register
Figure 4-16. SRU_CLK4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1001111011110111
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0011110111101111
SRU_CLK3 (0x2433) Reset = 0x3DEF7BDE
DIT_HFCLK_I
IDP6_CLK_I
IDP7_CLK_I
IDP6_CLK_I
IDP5_CLK_I
IDP3_CLK_I
IDP4_CLK_I
Input Data Port Channel
6 Clock Input
SPDIF Oversampling
Clock Input
Input Data Port Channel
3 Clock Input
Input Data Port Channel
4 Clock Input
Input Data Port Channel
7 Clock Input
Input Data Port Channel
5 Clock Input
Input Data Port Channel
6 Clock Input
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1001111011110111
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0011110111101111
SPDIF_EXTPLLCLK_I
External 512 x FS PLL Clock Input
PCG_EXTA_I
Precision Clock Generator
External Clock A Input
PCG_EXTB_I
Precision Clock Generator
External Clock B Input
SRU_CLK4 (0x2434)
Setting SRU_CLK4 4–0 = 28 connects PCG_EXTA_I to logic low, not to PCG_CLKA_O.
Setting SRU_CLK4 9–5 = 29 connects PCG_EXTB_I to logic low, not to PCG_CLKB_O.
PCG_SYNC_CLKB_I
Precision Clock Generator
Clock B Sync Input
Reserved
PCG_SYNC_CLKA_I
Precision Clock Generator
Clock A Sync Input
Reset = 0x3DEF7BDE
Reserved